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IRFP9140
Data Sheet July 1999 File Number
2292.4
19A, 100V, 0.200 Ohm, P-Channel Power MOSFET
This is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. It is a P-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17521.
Features
* 19A, 100V * rDS(ON) = 0.200 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance
Symbol
D
Ordering Information
PART NUMBER IRFP9140 PACKAGE TO-247 BRAND
G
IRFP9140
S
NOTE: When ordering, use the entire part number.
Packaging
JEDEC STYLE T0-247
SOURCE DRAIN GATE DRAIN (FLANGE)
4-57
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
IRFP9140
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified IRFP9140 -100 -100 -19 -12 -76 20 150 1.2 960 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Drain (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eas Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS
ID(ON)
TEST CONDITIONS VGS = 0V, ID = -250A, (Figure 10) VDS = VGS, ID = -250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON) MAX, VGS = -10V VGS = 20V VGS = -10V, I D = -10A, (Figures 8, 9) VDS -50V, ID = -10A, (Figure 12) VDD = -50V, ID -19A, RG = 9.1, RL = 2.5, VGS = -10V, (Figures 17, 18) MOSFET Switching Times Are Essentially Independent of Operating Temperature VGS = -10V, ID = -19A, VDS = 0.8 x Rated BVDSS, IG(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = -25V, f = 1.0MHz, (Figure 11)
MIN -100 -2.0 -19 5.3 -
TYP 0.14 7.9 16 65 47 28 37 8.7 22 1200 570 160 5.0
MAX -4.0 25 250 100 0.20 20 100 70 70 55 -
UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance
IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD
Measured Between Contact Screw on Header That Is Closer to Source and Gate Pins and Center of Die Measured From the Source Pin, 6mm (0.25in) From Header and Source Bonding Pad
Modified MOSFET Symbol Showing the Internal Device Inductances
D LD G LS S
-
Internal Source Inductance
LS
-
13
-
nH
Junction to Case Junction to Ambient
RJC RJA Free Air Operation
-
-
0.83 30
oC/W
0C/W
4-58
IRFP9140
Source to Drain Diode Specifications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D
MIN -
TYP -
MAX -19 -76
UNITS A A
S
Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES:
VSD trr QRR
TJ = 25oC, ISD = -19A, VGS = 0V, (Figure 13) TJ = 25oC, ISD = -18A, dISD/dt = 100A/s TJ = 25oC, ISD = -18A, dISD/dt = 100A/s
-
210 2.0
-1.5 -
V ns C
2. Pulse test: pulse width 80s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, start TJ = 25oC, L = 4.2mH, RG = 25, peak IAS = 19A. See Figures 15, 16.
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8
Unless Otherwise Specified
20
ID, DRAIN CURRENT (A) 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150
16
12
0.6 0.4
8
0.2 0
4
0 25
50
75 100 125 TC, CASE TEMPERATURE (oC)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
1 0.05 THERMAL IMPEDANCE 0.2 0.1 0.1 0.05 0.02 0.01 10-2 SINGLE PULSE PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ= PDM x ZJC x RJC + TC 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) 1 10 ZJC, NORMALIZED
10-3 10-5
FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE
4-59
IRFP9140 Typical Performance Curves
100 IDS, DRAIN TO SOURCE CURRENT (A) 100s 1ms IDS, DRAIN TO SOURCE CURRENT (A) 10s
Unless Otherwise Specified (Continued)
30
VGS = -10V VGS = -8V VGS = -7V
24
10 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 VDS, DRAIN VOLTAGE (V)
18
VGS = -6V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -5V
10ms 100ms DC
12
6 VGS = -4V 0 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) -50
0.1
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
30 IDS, DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 24 VGS = -8V 18 VGS = -7V VGS = -6V 12 VGS = -5V 6 VGS = -4V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 VGS = -10V
102
VDS -50V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
10
1 TJ = 150o TJ = 25o
0.1 0 2 4 6 8 VGS, DRAIN TO SOURCE VOLTAGE (V) 10
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
1.5
rDS(ON), DRAIN TO SOURCE ON RESISTANCE ()
1.2
VGS = -10V
NORMALIZED DRAIN TO SOURCE ON
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
3.0
2.4 RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V
0.9
1.8
0.6
1.2
0.3
VGS = -20V
0.6
0
0
16
32 48 ID, DRAIN CURRENT (A)
64
80
0 -60
-40
-20
0
20
40
60
80
100 120 140 160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4-60
IRFP9140 Typical Performance Curves
1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN ID = 250A 1.15 C, CAPACITANCE (pF) 2000
Unless Otherwise Specified (Continued)
2500
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
1.05
1500 CISS 1000 COSS
0.95
0.85
500 CRSS
0.75 -60
-40
-20
0
20
40
60
80
100 120 140 160
0
1
TJ, JUNCTION TEMPERATURE (oC)
10 NEGATIVE VDS, DRAIN TO SOURCE VOLTAGE (V)
102
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
15 gfs, TRANSCONDUCTANCE (S)
ISD, SOURCE TO DRAIN CURRENT (A)
12
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS -50V
-100 TJ = 150oC -10
9
TJ = 25oC
6
TJ = 150oC
TJ = 25oC -1.0
3
0
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 NEGATIVE VSD, SOURCE TO DRAIN VOLTAGE (V) -1.8
0
8
24 32 16 NEGATIVE ID, DRAIN CURRENT (A)
40
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = -19A
VGS, GATE TO SOURCE VOLTAGE (V)
16
VDS = -80V VDS = -50V VDS = -20V
12
8
4
0
0
12 24 36 48 Qg(TOT), TOTAL GATE CHARGE (nC)
60
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
4-61
IRFP9140 Test Circuits and Waveforms
VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0
+
VDD VDD
0V VGS
DUT tP IAS 0.01
IAS tP BVDSS VDS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr RL 0 10%
tOFF td(OFF) tf 10%
DUT VGS RG
VDD
+
VDS VGS 0
90%
90%
10% 50% PULSE WIDTH 90% 50%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
-VDS (ISOLATED SUPPLY)
0 VDS
DUT 12V BATTERY 0.2F 50k 0.3F Qgs D G 0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR DUT Qgd Qg(TOT) VDD 0 VGS
IG(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
4-62
IRFP9140
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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